The Challenge:

Our team supports critical defense and national security customers in the development of advanced and next generation aircraft, spacecraft, and more! This position will give you unique insight and exposure to a wide range of next generation microelectronics systems and designs being built across the defense community. These systems face challenges related to Design Verification, Trust, and Integrity, particularly related to third-party IP.

This position will include performing Universal Verification Methodology (UVM) on application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and system on chip (SoC) designs, including developing highly reusable UVM test benches, implementing coverage-driven verification methodologies and directed testing, and helping our verification team to drive quality, security, and integrity of microelectronics designs. In this role, you will lead ASIC, FPGA, and SoC verification activities for critical defense and national security systems. You will implement coverage-driven and directed testing to help the team drive the quality, security, and integrity of systems.

Empower change with us.

You Have:

-5+ years of experience with hands on UVM on ASIC, FPGA, or SoC designs in a lab, academic, commercial, or government environment

-Experience with developing System Verilog Test Benches using a UVM methodology from scratch

-Experience with developing and establishing design verification methodologies

-Experience with constrained random testing and coverage driven verification

-Experience with the verification of embedded processor cores and Intellectual Property (IP) cores

-Experience with Cadence or Mentor design and verification tools, including design verification planning and tracking tools, such as vManager

-Knowledge of System Verilog and UVM and OVM

-Ability to train other members of the team on UVM and other design verification techniques

-Ability to obtain a security clearance

-BA or BS degree in Engineering or CS

Nice If You Have:

-Experience with Formal Verification tool kits, including Cadence JasperGold or similar

-Experience with defense-related designs and relevant open source designs, including RISC-V

-Knowledge of System C or C/C++ and Python or Perl

-Active Secret clearance

-MA or MS degree in EE, CS, or a related engineering field

Clearance:

Applicants selected will be subject to a security investigation and may need to meet eligibility requirements for access to classified information.

We’re an EOE that empowers our people—no matter their race, color, religion, sex, gender identity, sexual orientation, national origin, disability, veteran status, or other protected characteristic—to fearlessly drive change.